Read Newsletter<\/p>\n
![\"TCVLSI](\"https:\/\/ieeecs-media.computer.org\/wp-media\/2022\/12\/08235241\/TCVLSI-November-2022-Newsletter.jpg\")
<\/p>\n
Excited to publish and share with the VLSI global community our TCVLSI Volume 8 Issue 4 newsletter, the eighth in my role as the IEEE-TCVLSI Chair. The Nov 2022 TCVLSI newsletter features an invited article.<\/p>\n
\u201cExperiential VLSI for Undergraduate Curriculum\u201d by Prof Arijit Raychowdhury Dept Chair of ECE at Georgia Tech, where while discussing the challenges, underscores the importance of an undergraduate curricular structure that provides students hands-on experience in designing, taping-out and measuring silicon as part of the degree requirement.<\/p>\n
The newsletter spotlights one of TCVLSI\u2019s sponsored symposiums in 2022 IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). One-page teasers of the best paper awarded at ASAP 2022 and three best paper nominees are showcased: \u201cAnswer Fast: Accelerating BERT on the Tensor Streaming Processor\u201d; \u201cHPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming\u201d; \u201cLOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models\u201d; \u201cEfficient Synchronization for NR-REDCAP Implemented on a Vector DSP\u201d.<\/p>\n
In a continuation of our Women in VLSI (WiV) series, we share an inspiring interview with Prof. Sandhya Dwarkadas, Walter N. Munster Professor and Chair of Computer Science Department at University of Virginia Additionally, included is a section on relevant recent announcements collated by our Associate Editor, Ishan Thakkar. The newsletter cover is designed by Dr. Olivier Franza. I\u2019d love to hear from the readers on what you would like to see in the subsequent newsletters. Feel free to provide any feedback\/recommendations via email to me. Happy reading.<\/p>\n<\/p><\/div>\n